Currently, various companies produce many modifications and analogues of this family, both by Intel and other manufacturers, the clock speed and memory capacity have increased tenfold and continue to increase. The set of modules built into the LSI is also being expanded; a large number of modern models have a built-in resident high-speed ADC with up to 12, and now there may be more, bits. But the MCS51 family is based on Intel LSIs 8051, 80С51, 8751, 87С51, 8031, 80С31, the first samples of which were released in 1980.
Microcontrollers of the MCS51 family are made using high-quality n-MOS technology (series 8ХХХ, analogue - series 1816 in Russia and Belarus) and k-MOS technology (series 8ХСХХ, analogue - series 1830). The second character following 8 means: 0 – there is no EPROM on the chip, 7 – a 4K EPROM with ultraviolet erasure. Third character: 3 – on-chip ROM, 5 – if there is no ROM, then there is a mask ROM on the chip.
And so 80С51 is an LSI based on k-MOS technology with a mask ROM on the chip, 8031 is an n-MOS LSI without program memory (ROM, RPOM) on a chip, 8751 is an n-MOS LSI with a resident (located on the chip) RPOM with ultraviolet erasing. We will further consider the 8751 LSI, making, if necessary, reservations about the differences between other circuits, citing those parameters that were published for the first serial LSIs. If necessary, you can find additional information about all modern modifications in company directories and technical documentation.
A. General characteristics and pin assignments
The MCS51 family is based on five modifications of the MK (having identical basic characteristics), the main difference between which is the implementation of program memory and power consumption (see Table 3.1). The microcontroller is eight-bit, i.e. has commands for processing eight-bit words, has a Harvard architecture, the clock frequency of the basic samples of the family is 12 MHz.
Table 3.1.
|
Micro circuits |
Internal program memory, bytes |
Program memory type |
Internal data memory, byte |
Clock frequency, MHz |
Current consumption, mA |
MK 8051 and 80C51 contain a mask-programmable ROM program memory with a capacity of 4096 bytes during the manufacture of the chip and are designed for use in mass production. MK 8751 contains a 4096-byte RPOM with ultraviolet erasure and is convenient at the system development stage when debugging programs, as well as during production in small batches or when creating systems that require re-writing during operation.
periodic adjustment.
MK 8031 and 80C31 do not contain built-in program memory. They, like the previously described modifications, can use up to 64 KB of external program memory and are effectively used in systems that require a significantly larger volume (than 4 KB on the chip) of ROM program memory.
Each MK of the family contains a resident data memory with a capacity of 128 bytes with the ability to expand the total amount of RAM data up to 64 KB through the use of external RAM ICs.
eight-bit central processor;
4 KB program memory (8751 and 87C51 only);
128 byte data memory;
four eight-bit programmable I/O ports;
two 16-bit multi-mode timer/counters;
auto-vector interrupt system with five vectors and two software-controlled priority levels;
serial interface, including a universal duplex transceiver capable of operating in four modes;
clock generator.
The MK command system contains 111 basic commands with a format of 1, 2, or 3 bytes. The microcontroller has:
32 general purpose registers RON, organized as four banks of eight registers each with names R0... R7, the choice of one bank or another is determined by the program by setting the corresponding bits in the program status register PSW;
128 software-controlled flags (bit processor, see below);
a set of registers of special functions that control MK elements. There are the following operating modes of the microcontroller:
1). General reset. 2).Normal functioning. 3).Low power consumption mode and idle mode. 4). Programming mode for resident RPOM, if available.
Here we will focus on the first two operating modes; a detailed description of the composition and operation of the MK in all modes is given in Appendix P1.
The RON and the bit processor area are located in the address space of the resident RAM with addresses from 0 to 80h.
In the upper zone of the residential RAM addresses there are special function registers (SFR, Special Function Registers). Their purpose is given in table. 3.2.
Table 3.2.
|
Designation |
Name | |
|
Battery | ||
|
Register B | ||
|
Program Status Register | ||
|
Stack pointer | ||
|
Data pointer. 2 bytes: | ||
|
Low byte | ||
|
High byte | ||
|
Interrupt Priority Register | ||
|
Interrupt enable register | ||
|
Timer/Counter Mode Register | ||
|
Timer/Counter Control Register | ||
|
Timer/counter 0. High byte | ||
|
Timer/counter 0. Low byte | ||
|
Timer/counter 1. High byte | ||
|
Timer/counter 1. Low byte | ||
|
Serial Port Control | ||
|
Serial Buffer | ||
|
Consumption management |
* - registers, allowing bitwise addressing
Let's briefly look at the functions of the SFR registers shown in Table 3.2.
Battery ACC - accumulator register. Commands designed to work
you with the battery, use the mnemonic "A", for example, MOV A, P2 . The ACC mnemonic is used, for example, when bitwise addressing an accumulator. Thus, the symbolic name of the fifth bit of the accumulator when using the A5M51 assembler will be as follows: ACC. 5. .
Register IN . Used during multiplication and division operations. For other instructions, register B can be treated as an additional real-time register.
Register state programs P.S.W. contains information about the state of the program and is installed partly automatically based on the result of the operation performed, and partly by the user. The designation and purpose of the register bits are given in Tables 3.3 and 3.4, respectively.
Table 3.3.
|
Designation |
Table 3.4.
|
Designation |
Bit assignment |
Bit Access |
||||
|
Carry flag. Changes during the execution of a series of arithmetic and logical instructions. |
Hardware or software |
|||||
|
Additional carry flag. Set/cleared in hardware during addition or subtraction instructions to indicate a carry or borrow in bit 3 when the least significant nibble of the result (D0-D3) is generated. |
Hardware or software |
|||||
|
Flag 0. User defined flag. |
Programmatically |
|||||
|
Programmatically |
||||||
|
Working Register Bank Index |
Programmatically |
|||||
|
Bank 0 with addresses (00Н - 07Н) Bank 1 with addresses (08Н - 0FН) Bank 2 with addresses (10Н - 17Н) Bank 3 with addresses (18Н - 1FН) | ||||||
|
Overflow flag. Set or cleared by hardware during execution of arithmetic instructions to indicate an overflow condition |
Hardware or software |
|||||
|
Spare. Contains a writable and readable trigger that can be used | ||||||
|
Parity bit. Hardware reset or set on each instruction cycle to indicate an even or odd number of battery bits in the "1" state. |
Hardware or software |
|||||
Pointer stack SP - An 8-bit register whose contents are incremented before writing data to the stack when PUSH and CALL instructions are executed. On initial reset, the stack pointer is set to 07H and the stack area in the data RAM starts at address 08H. If necessary, by overriding the stack pointer, the stack area can be located anywhere in the internal RAM of the microcontroller data.
Pointer data DPTR consists of a high byte (DPH) and a low byte
(DPL). Contains a 16-bit address when accessing external memory. Can be used
be either a 16-bit register or two independent eight-bit registers.
Port0 - PortZ. Separate bits of the registers of special functions P0, P1, P2, RZ are the “latches” bits of the ports P0, P1, P2, RZ.
Buffer consistent port SBUF represents two separate registers: the transmitter buffer and the receiver buffer. When data is written to the SBUF, it enters the transmitter buffer, and writing a byte to the SBUF automatically initiates transmission through the serial port. When data is read from SBUF, it is fetched from the receiver buffer.
Registers timer. Register pairs (TH0, TL0) and (TH1, TL1) form 16
bit counting registers for timer/counter 0 and timer/counter 1, respectively.
Registers management. Registers of special functions IP, IE, TMOD, TCON, SCON and PCON contain control bits and status bits of the interrupt system, time-
meters/counters and serial port. They will be discussed in detail below.
RxD TxD INT0 INT1 T0 T1 WR
P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
RST BQ2 BQ 1 E.A.
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
When functioning, the MC provides:
the minimum execution time for addition commands is 1 μs;
hardware multiplication and division with a minimum execution time of 4 μs.
The MK provides the ability to set the frequency of the internal oscillator using quartz, an LC chain or an external oscillator.
The extended instruction system provides byte and bit addressing, binary and binary decimal arithmetic, overflow indication and even/odd determination, and the ability to implement a logical processor.
The most important and distinctive feature of the MCS51 family architecture is that the ALU can manipulate single-bit data in addition to performing operations on 8-bit data types. Individual software-accessible bits can be set, cleared, or replaced by their complement, can be forwarded, checked, and
Fig.3.2. External pins
microcontroller
used in logical calculations. Whereas support for simple data types (if available)
While the current trend toward longer word lengths may seem like a step backward at first glance, this quality makes the MCS51 family of microcontrollers particularly suitable for controller-based applications. The operating algorithms of the latter presuppose the presence of input and output Boolean variables, which are difficult to implement using standard microprocessors. All these properties are collectively called the Boolean processor of the MCS51 family. This powerful ALU makes the MCS51 family of microcontrollers suitable for both real-time control applications and data-intensive algorithms.
The circuit diagram of the microcontroller is shown in Fig. 3.2. In the basic version, it is packaged in a 40-pin DIP package. Let's look at the purpose of the pins.
Let's start with the power pins «0 IN" And "5 IN" , through which he receives basic nutrition. Current consumption is given in table. 3.1.
Conclusion "RST" - microcontroller reset. When an active high level is applied to this pin, the mode general reset and MK performs the following actions:
Sets the PC program counter and all special function registers, except for the P0-P3 port latches, the SP stack pointer and the SBUF register, to zero;
the stack pointer takes the value equal to 07H;
disables all interrupt sources, timer-counter and serial
selects BANK 0 RAM, prepares ports P0-RZ for receiving data and determining
shares ALE and PME pins as inputs for external clocking;
in the special function registers PCON, IP and IE, the reserved bits take random values, and all other bits are reset to zero;
the SBUF register is set to random values.
sets the latches of ports P0-PZ to "1".
The states of the microcontroller registers after reset are shown in Table 3.5.
Table 3.5.
|
Information |
|
|
Uncertain |
|
|
0ХХХ0000V for k-MOS 0XXXXXXXB for n-MOS |
The RST pin also has an alternative function. Backup power is supplied through it to keep the contents of the microcontroller RAM unchanged when the main one is removed.
conclusions BQ1, BQ2 – are intended for connecting a quartz resonator that determines the clock frequency of the MK.
Conclusion EA` (E xternal A dress – external address) - designed to activate the mode of reading control codes from external program memory when an active low level is applied to this pin. The output has an alternative purpose (function). It is supplied with programming voltage from the RPOM in programming mode.
Conclusion PME (P rogram M emory E nable – permission memory programs) - is designed to control the cycle of reading from program memory and is automatically activated by the MK in each machine cycle.
Conclusion ALE (A dress L ength E nable – permission junior addresses) strobes the output of the low-order part of the address via port P0. The output is also used when programming the RPOM, while a strobe pulse for the programming process is supplied to it.
The MK contains four groups of ports: P0, P1, P2, and P3. These are the remaining 40 pins of the microcontroller. These ports can serve for bit-by-bit input and output of information, but in addition, each of them has its own specialization. A generalized functional diagram of the port is shown in Fig. 3.3. The port contains FET output switches connected to the pin, a function switch, a D flip-flop latch, and control logic. A unit or zero can be written to the latch on the internal bus of the MK. This information is sent through the function switch to the output switches and the output of the MK. In the one state, both transistors N and N1 are closed, but N2 is open. In the zero state N opens-
Xia, and N2 closes. The moment a port performs an alternative function for which it is specialized, the output latch state is cleared. The microcontroller can separately read the state of the port latch and the state of its output, set by an external signal. For this purpose, the MK assembler contains special commands that activate the corresponding lines. To read the pin state into the corresponding port latch, the
be pre-recorded
From internal
Control Latch
Function switch
Vcc 
Weekend
unit. When the “read latch” line is activated, the output of the “AND” cell to which this line is connected appears.
her tires MK D Q
Write to latch C Q
Read latch
Port pin
The latch state is transmitted to the internal bus of the MC when activated
“read output” - the state of the external pin of the port.
Port P0 – universal bidirectional port
I/O Beyond this port
the function of organizing external address buses and
Rice. 3.3. Functional diagram of the microcontroller port
data for expanding program memory and data memory
microcontroller. When the external program memory is accessed or a command is executed to access the external data memory, the low-order part of the address (A0...A7) is set at the port pins, which is gated high at the ALE pin. Then, when writing data to memory, the recorded information from the internal bus of the MK is sent to the pins of the P0 port. In read operations, on the contrary, information from the port pins is sent to the internal bus. A feature of the P0 port is the absence of a “pull-up” transistor N2, which provides power to the output. When writing to the unit port latch, it is simply transferred to a high-impedance state, which is necessary for normal operation of the data bus. If it is necessary to power any external devices through the output, external resistors should be provided from the power circuits to the port output.
Port P1 – universal bidirectional I/O port without alternative functions.
Port P2 – a universal bidirectional I/O port, which, as an alternative function, issues the high part of the address (A8...A15) when accessing external memory.
Port P3 – a universal bidirectional I/O port, each bit of which provides for the implementation of various alternative functions. In this case, alternative functions are implemented only if ones are written to the latches of the port pins; otherwise, the execution of alternative functions is blocked. Let us list them separately for each bit:
P3.0 – RxD (R ead e X internal D ate, read external data) – input of the built-in serial transceiver.
P3.1 – TxD (T ype e X internal D ate, transmit external data) – output of the built-in serial transceiver.
P3.2 – INT0` (INT errupt, interrupt) – external interrupt input 0.
P3.3 – INT1` – external interrupt input 1.
P3.4 – С/T0 – zero built-in timer/counter input.
P3.5 – C/T1 – input of the first built-in timer/counter.
P3.6 – WR` (W rite, write) – output for controlling the write cycle in the data memory.
P3.7 – RD` (R ead, read) – control output of the read cycle from data memory.
The pins of port P1, P2 and P3 are capable of outputting a current of about 0.2 mA per unit and receiving a current of 3 mA at zero; the pins of port P0 are more powerful and are capable of delivering a current of about 0.8 mA in one unit and receiving a current of 5 mA at zero. Brief information about the purpose of the microcontroller pins is given in Table 3.6.
Table 3.6.
|
Designation |
Output purpose | ||
|
8-bit bidirectional port P1. Address input A0-A7 when checking internal ROM (RPM) |
enter exit |
||
|
General reset signal. RAM backup power output from an external source (for 1816) | |||
|
8-bit bidirectional P3 port with additional features |
enter exit |
||
|
Receiver Serial Data - RxD | |||
|
Transmitter serial data - TxD | |||
|
External interrupt input 0-INT0` | |||
|
External interrupt input 1-INT1` | |||
|
Timer/counter input 0: - T0 | |||
|
Timer/counter input 1: - T1 | |||
|
Strobe signal output when writing to external data memory: - WR` | |||
|
Strobe signal output when reading from external data memory – RD` | |||
|
Leads for connecting a quartz resonator. |
exit input |
||
|
General conclusion | |||
|
8-bit bidirectional port P2. Address A8-A15 output in external memory mode. In the internal ROM check mode, pins P2.0 - P2.6 are used as the input of addresses A8-A14. Pin P2.7 - ROM reading permission. |
enter exit |
||
|
Program Memory Resolution | |||
|
Address fixation enable output signal. When programming the RPOM signal: PROG |
enter exit |
||
|
Blocking work with internal memory. When programming the RPOM, the UPR signal is given |
enter exit |
||
|
8-bit bidirectional port P0. Address/data bus for working with external memory. Data output D7-D0 in internal ROM (RPM) test mode. |
enter exit |
||
|
Power output from +5V voltage source |
The architecture of the MCS-51 family is largely determined by its purpose - the construction compact And cheap digital devices. All microcomputer functions are implemented using a single microcircuit. The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. Microcontrollers of the MCS-51 family allow you to perform both control tasks for various devices and implement individual components of an analog circuit. All microcircuits of this family work with the same command system, most of them are carried out in identical cases with matching pinout(numbering of legs for the body). This allows you to use microcircuits from different manufacturers (such as Intel, Dallas, Atmel, Philips, etc.) for the developed device. without altering the circuit diagram of the device and program.
Figure 1. Block diagram of the K1830BE751 controller
The block diagram of the controller is presented in Figure 1. and consists of the following main functional units: control unit, arithmetic-logical unit, timer/counter unit, serial interface and interrupt unit, program counter, data memory and program memory. Two-way communication is carried out using an internal 8-bit data bus. Let's take a closer look at the purpose of each block. Almost all members of the MCS-51 family are built according to this scheme. Various microcircuits of this family differ only in special-purpose registers (including the number of ports). Command system all controllers The MCS-51 family contains 111 basic instructions with a format of 1, 2 or 3 bytes and does not change when moving from one chip to another. This ensures excellent program portability from one chip to another.
Control and synchronization unit
The Timing and Control unit is designed to generate synchronizing and control signals that ensure coordination of the joint operation of the mainframe computer units in all permissible modes of its operation. The control unit includes:
- device for forming time intervals,
- input-output logic,
- command register
- energy management register,
- command decoder, computer control logic.
Device for forming time intervals designed for generating and issuing internal clock signals of phases, clocks and cycles. The number of machine cycles determines the duration of instructions. Almost all computer commands are executed in one or two machine cycles, except for multiplication and division instructions, the execution duration of which is four machine cycles. Let us denote the frequency of the master oscillator by F g. Then the duration of the machine cycle is equal to 12/F g or is 12 periods of the master oscillator signal. I/O logic is designed to receive and output signals that ensure the exchange of information with external devices through the input/output ports P0-P3.
Command Register designed to record and store the 8-bit operation code of the command being executed. The operation code, with the help of commands and computer control logic, is converted into microprogram for executing the command.
Demand Control Register (PCON) allows you to stop the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and interference can be achieved by stopping the microcontroller master oscillator. This can be achieved by toggling the bits of the PCON consumption control register. For the n-MOS manufacturing option (1816 series or foreign chips that do not have a “c” in the middle of their name), the PCON consumption control register contains only one bit that controls the baud rate of the serial port SMOD, and there are no power consumption control bits.
Together with the article "Architecture of microcontrollers MCS-51" read:
http://site/MCS51/tablms.php
http://site/MCS51/SysInstr.php
http://site/MCS51/port.php
Intel is the founder of the MCS-51 family architecture, which takes its name from the first representative of this family - the 8051 microcontroller, released in 1980 based on n-MOS technology. A successful set of peripheral devices, the ability to flexibly select external or internal program memory, and an affordable price ensured this microcontroller's success in the market. From a technology point of view, the 8051 microcontroller was a very complex product for its time - 128 thousand transistors were used in the crystal, which was 4 times the number of transistors in the 16-bit 8086 microprocessor. This microcontroller remains the core of the MCS-51 family to this day.
The main elements of the basic architecture of the family (8051 microcontroller architecture) are:
8-bit ALU;
4 banks of registers, 8 in each;
Internal (resident) program memory 4 KB, type ROM or EPROM (8751);
Internal (resident) data memory 128 bytes;
21 special function registers;
Boolean processor;
Two 16-bit timers/counters;
Serial port controller (UART);
Interrupt controller with two priority levels;
Four 8-bit I/O ports, two of which are used as an address/data bus for accessing external program and data memory;
Built-in clock generator.
Then the 8052 microcontroller was released, which featured an increased amount of resident program and data memory, a third timer, and a correspondingly expanded interrupt controller.
The next fundamental step in the development of the MCS-51 was the transfer of manufacturing technology to CMOS (modification 8xC51). This made it possible to implement Idl (idle) and Power Down (reduced consumption) modes, which provide a sharp reduction in the power consumption of the crystal and paved the way for the use of the microcontroller in power-dependent applications, for example, in stand-alone battery-powered devices.
And the last important stage in the development of the 8051 MK by Intel was the release of microcontrollers 8xC51FA/FB/FC and 8xC51RA/RB/RC, which for brevity are often referred to as 8xC51Fx and 8xC51Rx. The main distinguishing feature of this group of crystals is the presence of a specialized timer/counter (SCA). In addition, the 8xC51Rx microcontrollers additionally contain a watchdog timer (WDT). Let's look at the architecture and functionality of PCA in more detail.
The RSA includes:
16-bit timer/counter;
Five 16-bit sample and compare modules, each connected to its own microcontroller I/O port line.
The timer/counter serves all five sample and compare modules, which can be programmed to perform one of the following functions:
16-bit sampling of the timer value on the positive edge of an external signal;
16-bit sampling of the timer value on the negative edge of an external signal;
16-bit sampling of the timer value on any edge of an external signal;
16-bit programmable timer;
16-bit high-speed output device;
8-bit PWM.
All of the above functions are performed in PCA at the hardware level and do not load the central processor. This allows you to increase the overall throughput, improve the accuracy of measurements and signal processing, and reduce the microcontroller’s response time to external events, which is especially important for real-time systems. The PCA implemented in 8xC51Fx (8xC51Rx) turned out to be so
|
Designation |
Max. frequency (MHz) |
ROM/EPROM (byte) |
counters | ||
It was fortunate that the architecture of these microcontrollers became an industry standard, and the PCA itself was reproduced many times in various modifications of the MK 8051.
Some characteristics of a number of MCS-51 microcontrollers manufactured by Intel are given in Table 1.1.
Initially, the biggest bottlenecks of the MCS-51 architecture were the 8-bit battery-based ALU and relatively slow instruction execution (the fastest instructions require 12 processors to execute).
Table 1.1
|
I/O |
ADC, inputs x bits |
periphery, peculiarities |
U power (IN) |
||
|
Low voltage option | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
|
Low voltage version 8xC51Fx | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
|
4 levels IRQ, clock out | |||||
clock frequency periods (MK synchronization frequency)). This limited the use of microcontrollers of the family in applications requiring increased speed and complex calculations (16- and 32-bit). The issue of fundamental modernization of the MCS-51 architecture has become urgent. The problem of modernization was complicated by the fact that by the beginning of the 90s a lot of developments had already been created in the field of software and hardware of the MCS-51 family, and therefore one of the main tasks of designing a new architecture was the implementation of hardware and software compatibility with developments based on MCS -51.
To solve this problem, a joint group of specialists from Intel and Philips was created, but later the paths of these two companies diverged. As a result, in 1995, two significantly different families appeared: MCS-251/151 from Intel and MCS-51XA from Philips (see subsection 1.2).
Main characteristics of the MCS-251 architecture:
24-bit linear address space, addressing up to 16 MB of memory;
Register architecture that allows registers to be accessed as bytes, words, and doublewords;
Page addressing mode to speed up fetching instructions from external program memory;
Instruction queue;
Extended instruction set, including 16-bit arithmetic and logical operations;
Extended stack address space (up to 64 KB);
Execute the fastest command in 2 clock cycles.
The MCS-251 instruction set includes two instruction sets - the first set is a copy of the MCS-51 instruction set, and the second consists of extended instructions that take advantage of the MCS-251 architecture. Before using the microcontroller, it must be configured, i.e. using the programmer, “burn” the configuration bits that determine which set of instructions will become active after turning on the power. If you install the first set of instructions, then in this case the MCS-251 family will be compatible with the MCS-51 at the binary code level. This mode is called Binary Mode. If you initially install a set of extended instructions (Source Mode), then programs written for the MCS-51 will require recompilation using cross-tools for the MCS-251. Source Mode allows you to use the MCS-251 architecture with maximum efficiency and achieve the highest performance.
For users focused on using MCS-251 microcontrollers as a mechanical replacement for MCS-51, Intel produces MCS-151 microcontrollers already programmed in the Binary Mode state.
Some characteristics of a number of microcontrollers MCS-251/151 are given in Table 1.1.
Currently, Intel, aimed at the Pentium processor market, is curtailing the production of MCS-51 crystals. In general, for a particular developer this may go unnoticed, unless he uses 8xC51GB and 80C152Jx microcontrollers, which do not have their exact analogues among products from other companies. As for all the other microcontrollers of the MCS-51 family, they have all been replicated many times by other companies.
The basis of the microcontroller (see Fig. 1) is an 8-bit Arithmetic Logic Unit (ALU). The MK memory has Harvard architecture, i.e. logically divided into: program memory - PP (internal or external), addressed by a 16-bit program counter (SC) and data memory - internal (Resident Data Memory - RPD) 128 (or 256) bytes, as well as external (External Data Memory – VPD) up to 64 KB. Physically, program memory is implemented in ROM (read-only), and data memory is implemented in RAM (data can be written and read).
Reception and output of external signals is carried out through 4 eight-bit ports P0..P3. When accessing external program memory (EPM) or data memory (DRAM), ports P0 and P2 are used as a multiplexed external Address/Data bus. P3 port lines can also perform alternative functions (see Table 1).
The 16-bit DPTR register forms the VPD address or base address of the Program Memory in the Accumulator conversion command. The DPTR register can also be used as two independent 8-bit registers (DPL and DPH) to store operands.
The 8-bit internal command register (RC) receives the code of the command being executed; this code is deciphered by the control circuit, which generates control signals (see Fig. 1).
Access to special function registers - RSF (SFR - in Fig. 1 they are circled with a dotted line) is possible only using direct byte addressing in the address range from 128 (80h) and more.
The resident data memory (RDM) in the first models of microcontrollers of the MCS-51 family had a volume of 128 bytes. The lower 32 bytes of the RPD are also general purpose registers - RON (4 banks of 8 RONs each). The program can contact one of the 8 RONs of the active bank. The selection of the active RON bank is carried out by programming two bits in the processor status register - PSW.
Table 1 – MCS–51 pin assignments
| Pin No. | Designation | Purpose |
| 1..8 | P1 | 8-bit quasi-bidirectional I/O port |
| 9 | RST | Reset signal (active level – high); The RST signal resets: the PC and most Special Function Registers (SFRs), disabling all interrupts and timers; selects RON Bank 0; writes “all ones” to ports P0_P3, preparing them for input; writes code 07H to the stack pointer (SP); |
| 10..17 | 8-bit quasi-bidirectional I/O port; after recording in the corresponding category “1” – performs additional (alternative) functions: Serial port input – RxD; Serial port output – TxD; External interrupt input 0 – ~INT0; External interrupt input 1 – ~INT1; Timer/counter input 0 – T0; Timer/counter input 1 – T1; Strobe output signal when writing to VPD – ~ WR; Strobe output signal when reading from the VPD – ~ RD; |
|
| 18, 19 | X1, X2 | Pins for connecting a quartz resonator or LC circuit; |
| 20 | GND | General conclusion; |
| 21..28 | P2 | 8-bit quasi-bidirectional I/O port; or address output A in the mode of operation with external memory (VPP or VPD); |
| 29 | PME | Strobe for reading External Program Memory, issued only when accessing external ROM; |
| 30 | ALE | External memory address strobe (VPP or VPD); |
| 31 | EA | Disabling the RPP, level “0” at this input transfers the MK to command sampling only from the runway ; |
| 39..32 | P0 | 8-bit bidirectional I/O port; when accessing External Memory, it issues addresses A (which are written to an external register using the ALE signal), and then exchanges a byte synchronously with the ~PME signal (for commands) or ~WR,~RD (for data in VPD), when accessing External Memory all units are written to the P0 port register, destroying the information stored there; |
| 40 | Ucc | Supply voltage output |
Switching RON banks simplifies the execution of subroutines and interrupt handling, because there is no need to send the contents of the RONs of the main program to the stack when calling a subroutine (it is enough to go to another active bank of RONs in the subroutine).
Access to the RPD is possible using indirect or direct byte addressing (direct byte addressing allows you to access only the first 128 bytes of the RPD).
The extended RPD area (for microcontrollers of the MCS-52 family and subsequent families) from address 128 (80h) to 255 (FFh) can only be addressed using the indirect addressing method.
Table 2 – Block of Special Function Registers (s f r)
| Mnemo code | Name | |
| 0E0h | * ACC | Battery |
| 0F0h | *B | Register accumulator expander |
| 0D0h | *PSW | Processor Status Word |
| 0B0h | *P3 | Port 3 |
| 0A0h | *P2 | Port 2 |
| 90h | *P1 | Port 1 |
| 80h | * P0 | Port 0 |
| 0B8h | *IP | Interrupt Priority Register |
| 0A8h | *IE | Interrupt Mask Register |
| 99h | SBUF | Serial Transceiver Buffer |
| 98h | * SCON | Serial Port Control/Status Register |
| 89h | TMOD | Timer/Counter Mode Register |
| 88h | * TCON | Timers/Counters Control/Status Register |
| 8Dh | TH1 | Timer 1 (high byte) |
| 8Bh | TL1 | Timer 1 (low byte) |
| 8Ch | TH0 | Timer 0 (high byte) |
| 8Ah | TL0 | Timer 0 (low byte) |
| 83h | DPH | Data Pointer Register (DPTR) (high byte) |
| 82h | DPL | Data Pointer Register (DPTR) (low byte) |
| 81h | SP | Stack pointer register |
| 87h | PCON | Power Consumption Control Register |
2. SOFTWARE MODEL MCS–51
MCS–51 COMMAND TYPES
Almost half of the instructions are executed in 1 machine cycle (MC). With a quartz oscillator frequency of 12 MHz, the execution time of such a command is 1 μs. The remaining instructions are executed in 2 machine cycles, i.e. in 2μs. Only the multiply (MUL) and divide (DIV) instructions are executed in 4 machine cycles.
During one machine cycle, two accesses to the Program Memory (internal or external) occur to read two bytes of a command or one access to the External Data Memory (EDM).
3. METHODS (WAYS) OF ADDRESSING MCS–51
1. REGISTER ADDRESSING – the 8-bit operand is located in the RON of the selected (active) register bank;
2 DIRECT ADDRESSING (indicated by the sign – #) – the operand is located in the second (and for a 16-bit operand in the third) byte of the command;
3 INDIRECT ADDRESSING (indicated by the sign – @) – the operand is located in the Data Memory (RDM or VPD), and the address of the memory cell is contained in one of the RONs of indirect addressing (R0 or R1); in PUSH and POP commands the address is contained in the stack pointer SP; the DPTR register can contain a VPD address of up to 64K;
4 DIRECT BYTE ADDRESSING – (dir) – is used to access RPD cells (addresses 00h...7Fh) and special function registers SFR (addresses 80h...0FFh);
5 DIRECT BITS ADDRESSING – (bit) – is used to access separately addressable 128 bits located in RPD cells at addresses 20H...2FH and to separately addressable bits of special function registers (see Table 3 and program model);
6 INDIRECT INDEX ADDRESSING (indicated by the sign – @) – simplifies viewing tables in Program Memory, the PP address is determined by the sum of the base register (PC or DPTR) and the index register (Accumulator);
7 IMPLICIT (BUILT-IN) ADDRESSING – the command code contains an implicit (by default) reference to one of the operands (most often to the Accumulator).
4. PROCESSOR STATUS WORD (PSW) FORMAT
C – carry (CARY) or borrow flag, also performs the functions of a “Boolean Accumulator” in commands operating with bits;
AC – auxiliary (additional) carry flag – is set to “1” if in the addition command (ADD, ADDC) there was a transfer from the low tetrad to the high tetrad (i.e. from the 3rd bit to the 4th bit);
F0 – user flag – set, reset and checked by software;
| RS1 | RS0 | Bank | Address (dir) |
| 0 | 0 | 0 | 00h..07h |
| 0 | 1 | 1 | 08h..0Fh |
| 1 | 0 | 2 | 10h..17h |
| 1 | 1 | 3 | 18h..1Fh |
RS1,RS0 – Register bank selection:
OV – Arithmetic overflow flag; its value is determined by the "Exclusive OR" operation of the input and output transfer signals of the most significant bit of the ALU; a single value of this flag indicates that the result of an arithmetic operation in two’s complement code is outside the permissible limits: –128…+127; when a division operation is performed, the OV flag is reset, and in the case of division by zero, it is set; when multiplying, the OV flag is set if the result is greater than 255 (0FFH);
PSW bit – Reserve, contains a trigger, accessible by writing or reading;
P – parity flag – is the addition of the number of unit bits in the accumulator to even; generated by a combinational circuit (software accessible only by reading).
MCS-51 microcontrollers do not have the "Z" flag. But in the conditional jump commands (JZ, JNZ), the current (zero or non-zero) contents of the Accumulator are checked by the combinational circuit.
All transfer and operand exchange commands can be carried out through the Accumulator (see Fig. 3). Moreover, transfers from/to External Memory (Program Memory or Data Memory) can only be carried out through the Battery.
Most transfers can also be done via a direct byte (dir). There are even dir–dir transfers (see Figure 3).
Missing transfers from RON to RON can be implemented as transfers from RON to a directly addressed byte dir (taking into account that RONs are located in the initial area of the Resident Data Memory, the cells of which can be addressed as dir).
XCH exchange instructions allow bytes to be transferred without destroying both operands.
Arithmetic instructions are executed only in the Accumulator. Therefore, the first operand must first be placed in the Accumulator and then add or subtract the second operand. The result is placed in the Accumulator.
The SUBB subtraction command is executed only with a loan (i.e., the Cary flag is also subtracted from the result). Therefore, to execute a subtract command without borrowing, you must first issue the C flag clear command (CLRC).
The instruction for multiplying single-byte operands - MULAB - places a two-byte (16 bit) result: the low byte in the Accumulator, the high byte in the B register.
The result of executing the command for dividing single-byte operands - DIVAB - is placed: the quotient - a Accumulator, the remainder - in register B.
The INC arithmetic instruction adds one to the selected operand. The DEC arithmetic instruction subtracts one from the selected operand. The Decimal Accumulator Adjustment (DAA) command helps you add binary coded decimal (BCD) numbers without converting them to hexadecimal format (hex format). The source operands must be in BCD format, i.e. Each tetrad of one byte contains only numbers from 0 to 9 (there cannot be hexadecimal numbers: A, B, C, D, E, F). Therefore, one byte can contain numbers from 00 to 99 for packed BCD numbers or numbers from 0 to 9 for unpacked BCD numbers.
The DA A - decimal correction command performs actions on the contents of the Accumulator after adding BCD numbers in the processor (the numbers were added according to the laws of hexadecimal arithmetic) as follows (see example):
· if the contents of the low tetrad of the Accumulator are greater than 9 or the auxiliary carry flag is set (AC = 1), then 6 is added to the contents of the Accumulator (i.e. the missing six digits in hex format);
· if after this the contents of the highest tetrad of the Accumulator are greater than 9 or flag C is set, then the number 6 is added to the highest tetrad of the Accumulator.
The decimal correction command DA A is not used after the increment command (INC) because the increment command does not affect (change) the C and AC flags.
Logical commands:
Logical "AND" - ANL,
Logical "OR" – ORL,
Logical XOR commands - XRL - are executed in the Accumulator (as are arithmetic ones), but it is possible to execute logical commands also in the direct byte (dir). In this case, the second operand can be:
In Battery or
The immediate operand of a command.
Rotation commands (RR A, RL A) and rotation commands via the CARY flag (RRC A, RLC A) cyclically shift the contents of the Accumulator by 1 bit. Transfers of bit operands are carried out only through the C flag.
- Arithmetic commands;
- Logical commands;
- Data transfer commands;
- Bit processor commands;
- Branching and control transfer commands.
- Register addressing
- Direct addressing
- Register-indirect addressing
- Direct addressing
- Indirect register addressing based on the sum of the base and index registers
| Designation, symbol | Purpose |
| A | Battery |
| Rn | Registers of the currently selected register bank |
| r | The number of the loaded register specified in the command |
| direct | Directly addressable 8-bit internal data cell address, which can be internal data RAM cell (0-127) or SFR (128-255) |
| @Rr | Indirectly addressable 8-bit internal data RAM cell |
| data8 | 8-bit immediate data going to the COP |
| dataH | Most significant bits (15-8) of the immediate 16-bit data |
| dataL | Least significant bits (7-0) of immediate 16-bit data |
| addr11 | 11-bit destination address |
| addrL | Least significant bits of destination address |
| disp8 | 8-bit offset byte with sign m |
| bit | A directly addressable bit whose address contains the COP located in the internal data RAM or SFR |
| a15, a14...a0 | Destination address bits |
| (X) | Contents of element X |
| ((X)) | Contents at the address stored in element X |
| (X)[M] | Bit M of element X |
| + - * / AND OR XOR /X | Operations: addition subtraction multiplication division logical multiplication (AND operation) logical addition (OR operation) addition modulo 2 (exclusive OR) inversion of element X |
Function mnemonics are uniquely associated with specific combinations of addressing methods and data types. In total, there are 111 such combinations possible in the command system. The table shows a list of commands, sorted alphabetically.
| Mnemonics | Function | Flags |
| ACALL command | Absolute subroutine call | |
| ADD A command<байт-источник> | Addition | AC, C, OV |
| ADDC A command<байт-источник> | Addition with carry | AC, C, OV |
| AJMP Team | Absolute transition | |
| Team ANL<байт-назначения>, <байт-источникa> | Logical "AND" | |
| ANL C Team,<байт-источникa> | Logical "AND" for bit variables | |
| CJNE Team<байт-назначения>, <байт-источник>, <смещение> | Compare and jump if not equal | C |
| CLR A command | Battery reset | |
| CLR command | Reset bit | C,bit |
| Team CPL A | Inversion of ak umulya ora | |
| CPL Team | Bit inversion | C,bit |
| Team DA A | Decimal accumulator correction for position | AC, C |
| DEC Team<байт> | Decrement | |
| Team DIV AB | Division | C, OV |
| Team DJNZ<байт>, <смещение> | Decrement and jump if not equal to zero | |
| Team INC<байт> | Increment | |
| INC DPTR command | Data pointer increment | |
| Team JB | Jump if bit is set | |
| JBC Team | Jump if bit is set and reset that bit | |
| Team JC | Transition if transfer is set | |
| Command JMP @A+DPTR | Indirect transfer | |
| Team JNB | Jump if bit is not set | |
| JNC Team | Jump if carry is not set | |
| JNZ Team | Jump if the accumulator contents are not zero | |
| Team JZ | Jump if the accumulator contents are 0 | |
| LCALL command | Long call | |
| LJMP Team | Long passage | |
| MOV command<байт-назначения>, <байт-источника> | Forward byte variable | |
| MOV command<бит-назначения>, <бит-источника> | Send data bit | C |
| Command MOV DPTR,#data16 | Load a data pointer with a 16-bit constant | |
| MOVC command A,@A+( | Send byte from program memory | |
| MOVX Team<байт приемника>, <байт источника> | Send data to external memory (from external memory) | |
| Team MUL AB | Multiplication | C, OV |
| NOP command | No operation | PC |
| ORL Team<байт-назначения>, <байт-источникa> | Logical "OR" for variable bytes | |
| ORL C Team,<бит источникa> | Logical "OR" for bit variables | C |
| POP command | Reading from the stack | |
| PUSH command | Writing to the stack | |
| RET command | Return from subroutine | |
| RETI Team | Return from interrupt | |
| Team RL A | Shift accumulator contents left | |
| RLC A Team | Shift the contents of the accumulator to the left via the carry flag | |
| RR A command | Shift the contents of the accumulator to the right | |
| RRC A Team | Shift the contents of the accumulator to the right via the carry flag | C |
| SETB command | Set bit | C |
| Team SJMP<метка> | Short transition | |
| Team SUBB A,<байт источника> | Subtraction with borrowing | AC, C, OV |
| SWAP A command | Exchange of notebooks inside the battery | |
| XCH A command,<байт> | Exchange the contents of the accumulator with a byte variable | |
| XCHD command A,@R1 | Exchange of notebooks | |
| XRL Team<байт-назначения>, <байт-источникa> | Logical "XOR" for byte variables |
